DRAM Idle Timer - co to znamena?

[msdr.mike]

manual k me P2B-F je opravdu sdilny - "prodleva mezi zavrenim a otevrenim page. nechte na default!" zajimalo by me, jak tato polozka ovlivni vykon pameti a cemu odpovida. vetsina lidi uvadi u pameti 2-2-2-5/7, odpovida tedy tato hodnota 5/7? mam k dispozici hodnoty 10T (by SPD), 8T (7ns), 4T, 2T, 0T

[msdr.mike]

odpovida tedy tato hodnota 5/7?

sam si odpovim: ne! prave jsem to nasel ... ale ten zbytek porad nevim

[LookAS]

ta prvni dvojka znamena CAS Latency (negdy psano jen CAS nebo CL), ty zbyly sou u kazdy desky v biosu pojmenovany jinak, kazdopadne to sou ty 2 ostatni volby, vetsinou v biosu hnedka pod CL, kde se da menit timing mezi 2/3.
btw da se napr psat i 2-2-5-2-4-8-4-1-8 (a ruzne zprehazeno) ale to uz je nadlouho to rozepisovat

[WeSTLeR]

Nerad bych kecal, ale nejagresivnejsi je pro DRAM Idle Timer 0T (jako zadna prodleva).

[WeSTLeR]

S trochou nadsazky by se dalo rict, ze cim nizsi hodnoty, tim vykonejsi, ale neplati to uplne vsude - napr. Burst Length (tam je to obracene) ...

[Rainbow]

Prave naopak, najrychlejsie je nastavenie INFINITE. Vtedy sa to nezatvara vobec.

[WeSTLeR]

Prave naopak, najrychlejsie je nastavenie INFINITE. Vtedy sa to nezatvara vobec.

No nevim, nekde jsem cetl ze prave NEKONECNO (infinite) je pomalejsi nez 0T ...

[msdr.mike]

podle hodnoty v Memtestu se pri Infinite snizi cca od 20MB/s u ostatnich hodnot se nemeni. Sandra taky zadny zmeny neukazuje (nebo tak maly, ze je nelze jednoznacne pricist zmene v casovani) takze to asi necham na 2T, chyby to nehazi ...

[Rainbow]

U mna je to prave pri Infinite rychlejsie. Vyzera ze to zavisi od pamati.

[msdr.mike]

Tak jsem udelal pokus -> Sandra + WPCREGEDIT:
max. vysledky pri 0T a Infinite. pri zvysovani (0T, 2T, ...) az po hodnotu 16T vysledek klesal, pak zase zacal stoupat.
mam problem, jak vubec spravne interpretovat definici: "This controls the idle clocks before closing an opened SDRAM page." - pocet nevyuzitych cyklu pred uzavrenim page

[Mymak]

This feature sets the number of idle cycles a SDRAM bank has to wait before recharging. It allows you to improve the efficiency of the SDRAM read and write cycles by adjusting the amount of time that the bank is allowed to remain idle before it is recharged.

Increasing the SDRAM Idle Limit to more than the default of 8 cycles allows the SDRAM bank to delay recharging longer during times of no activity so that if a read or write command comes along, it can be instantly satisfied.

However, this is limited by the refresh cycle already set by the BIOS. That means the SDRAM bank will refresh when it needs to be recharged whether the number of idle cycles have reached the SDRAM Idle Limit or not. So, the SDRAM Idle Limit setting can only be used to force the refreshing of the SDRAM bank before the set refresh cycle but not to actually delay the refresh cycle.

Reducing the number of cycles from the default of 8 cycles to 0 cycles forces the SDRAM bank to initiate a refresh cycle once no valid requests are sent to the memory controller. In short, the SDRAM bank is refreshed as soon as it is idle. Theoretically, this may increase the efficiency of the SDRAM as the effects of refreshing the banks are masked because they are done during idle cycles. However, if there are any data requests after the bank starts its refresh cycle, they will have to wait until the bank is completely refreshed and activated before they can be satisfied.

Because refreshes do not occur that often (usually only about once every 64 msec), the impact of refreshes on SDRAM performance is really quite minimal and the benefits of masking the SDRAM's refreshes during idle cycles will not be noticeable. In fact, there's a high risk that data requests will get stalled more often, especially with the idle limit of 0 cycle. As such, you are more likely to see reduced performance with the 0 cycles setting, especially since even a single idle cycle will cause the bank to go into a bandwidth-expensive refresh cycle. On the plus side, the contents of the memory cells will be refreshed more often and there will be little chance of losing data due to insufficiently refreshed memory cells.

For best performance, this feature should be disabled so that refreshing can be delayed for as long as possible. This reduces the number of refreshes and increases the effective memory bandwidth.

An alternative method would be to greatly increase the value of the Refresh Interval or Refresh Mode Select feature to boost bandwidth and use this feature to maintain the data integrity of the memory cells. As ultra long refresh intervals (i.e. 64 or 128 µsec) can cause memory cells to lose their contents, setting a low SDRAM Idle Limit like 0 or 8 cycles allows the memory cells to be refreshed more often, with a high chance of those refreshes being done during idle cycles. This appears to combine the best of both worlds - a long bank active period when the memory controller is being stressed and more refreshes when the memory controller is idle.

In reality though, this is a really unreliable way of ensuring sufficient refresh cycles since it depends on the vagaries of memory usage to provide sufficient idle cycles to trigger the refreshes. If your memory subsystem is constantly in heavy use, there may not be any idle cycles to trigger an early refresh. This will cause the memory cells to lose their contents because they are not being refreshed enough.

Therefore, it is recommended that you maintain a proper refresh interval and disable this feature. This will allow you to boost memory bandwidth by delaying refreshes for as long as possible and still maintain the data integrity of the memory cells via regular and reliable refresh cycles.