Mate pravdu zaklad je asi CISC ale jak jsem na to koukal je to fyzicky takej hybrídos

Both the Athlon and the P6 run the CISC x86 ISA in what amounts to hardware emulation, but they translate the x86 instructions into smaller, RISC-like operations that fed into a fully post-RISC core. Their cores have a number of RISC features (LOAD/STORE memory access, pipelined execution, reduced instructions, expanded register count via register renaming), to which are added all of the post-RISC features we've discussed. The Athlon muddies the waters even further in that it uses both direct execution and a microcode engine for instruction decoding. A crucial difference between the Athlon (and P6) and the G4 is that, as already noted, the Athlon must translate x86 instructions into smaller RISC ops.

In the end, I'm not calling the Athlon or P6 "RISC," but I'm also not calling them "CISC" either. The same goes for the G3 and G4, in reverse. Indeed, in light of what we now know about the the historical development of RISC and CISC, and the problems that each approach tried to solve, it should now be apparent that both terms are equally nonsensical when applied to the G3, G4, MIPS, P6, or K7. In today's technological climate, the problems are different, so the solutions are different. Current architectures are a hodge-podge of features that embody a variety of trends and design approaches, some RISC, some CISC, and some neither. In the post-RISC era, it no longer makes sense to divide the world into RISC and CISC camps.
je to celkem zajimavy... cim vic se v tom vrtam tim vic me to laka