Citace Původně odeslal ALFik
CPU jako Athlon jsou podle me zalozeny na architekture RISC (Reduced Instruction Set Computing) ale mozna se pletu...
No LOL

porad je to x86, tzn. ze je to v zakladu CISC kompatibilni s 8086 instrukcemi... Napr. i SIMD instrukce opravdu nejsou RISCove. Navenek to urcite neni RISC, co je uvnitr, nikoho (= programatory) nezajima.

Citace Původně odeslal http://www.duxcw.com/digest/guides/cpu/athlon/athlon.htm
The Athlon has three X86 instruction decoders. An instruction set is a processor's language. An instruction tells the processor what data to operate on and what to do with it. An X86 instruction varies in length from one to 15 bytes. A byte is eight bits; a bit is logical one or zero. A logical one or zero is represented respectively by two voltage levels or the two states of a transistorized electronic switch (on or off like a light switch; a 1 or 0 in the binary number system, which, in turn, can be used to represent characters, decimal numbers, instructions, etc.). The decoders convert X86 instructions into fixed-length MacroOPs, the language of the Athlon. In short, these decoders decode X86 instructions into Athlon instructions.
Jeste doporucuji precist si stranu 3 tohoto dokumentu: http://www.amd.com/us-en/assets/cont.../x86-64_wp.pdf

edit: Jinak chvalim AMD, ten dokument je opravdu pekne napsany a vystihuje pravou podstatu a stav veci ohledne x86_64.