Jak enablovat HT u P4(B), které to oficielně nepodporují ?

[Over]

téma a diskuze http://www.vr-zone.com/Home/news170/news170.htm#2749

[LookAS]

pockam si az to negdo zkusi

[Mymak]

http://www.overclockers.ru/news/news...&id=1042308469

[LookAS]

http://www.overclockers.ru/news/newsitem.shtml?category=1&id=1042308469

he, neprelozil bys mi to?

[Mymak]

http://www.overclockers.ru/news/newsitem.shtml?category=1&id=1042308469

he, neprelozil bys mi to?

Tak to bohuzel nezvladnu.

[Mymak]

PowerLeap na to dela redukci, ale asi bude dost mastna. Podrobnejsi schema:

http://www.powerleap.com/downloads/PL-iP4.pdf

[LookAS]

jj, o ty redukci vim, bavej se o ni na vr-zone.com

[MomoBrut]

http://www.overclockers.ru/news/newsitem.shtml?category=1&id=1042308469

he, neprelozil bys mi to?

Tak to bohuzel nezvladnu.

No na tom temer nic neni, ale jestli to funguje?

Je to spinac (invertor) s PNP (SE) tranzistorem. Kdyz bude uroven 0 na CPURST3, pujde na A31 uroven 1, jinak je A31 na 0.

Jeste by to chtelo popis tech dvou signalu ...

[MomoBrut]

No, tak jsem to nejak zkoumal, ten popis existuje. Po nejakou dobu musi byt behem startu na A31 uroven 1 a pak jen uroven 0. Coz resi ten tranzistor invertovanim signalu reset3.

A31# goes on pin number U4
http://www.intel.com/design/Pentium...ts/29864306.pdf
Page 67


quote:
--------------------------------------------------------------------------------
Power-On Configuration Pins"

Disable Hyperthreading Technology" A31

Asserting this signal during RESET# will select the corresponding option
--------------------------------------------------------------------------------

H_CPURST# is AB25

http://www.intel.co.jp/design/intar...gd/25131901.pdf

Its on a few pages, but RESET does this:


quote:
--------------------------------------------------------------------------------

RESET#

Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all sysem bus agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive transition of RESET# for power on configuration. These configuration options are descrived in the Section 6.1

This signal does not have on-die terminiation and must be terminated on the system board.
--------------------------------------------------------------------------------


Hmm, jestli to funguje se zjisti jen vyzkousenim. Samozrejme jeste musi byt BIOS, ktery u dane desky umozni nastaveni HT.

Jinak vetsina info je na www.vr-zone.com, ve foru nejaky Ristar o tom pise, ale rekl bych, ze spis mlzi, jenom keci ...

Nejlepsi bude pockat na test noveho Powerleapu pro P4, kdyz to s nim pojede, tak neni problem. Ale clovek z Powerleapu (tvaril se tak) tvrdil, ze to pojede jen z P4 3.04G. Pry je to jen uprava pro starsi MB, ktere puvodne HT nepodporovali.