PCI Latency Timer x8(clk)

[LM]

Moh by ste mi někdo vysvětlit co přesně tahleta popožka v BIOSu znamená (nejspíš to bude mít něco společnýho se spožděním PCI -> podle názvu )
Momentálně ji mam nastavenou na 4 (rozsah 0-31).

[Anonymous]

no asi takhle: kdyz nejaky zarizeni na pci jede v bus masteringu, tak tahle hodnota udava pocet cyklu, kdy muze takhle jet a obsazovat plne pci sbernici...pak to zarizeni musi sbernici uvolnit...
tady mas i original...

"How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data.

If the latency timer is set too low, PCI devices will interrupt their transfers unnecessarily often, hurting performance. If it's set too high, devices that require frequent bus access may overflow their buffers, losing data.

So in theory there's a compromise that can be reached somewhere in between, where all devices can get good performance plus a reasonable guarantee that they will get bus access on a timely basis."

v tvem pripade bych ji mozna dal na trochu vetsi hodnotu...tak 10, 12...ale pokud nepoznas rozdil ve vykonu nejakych karet na PCI tak je to jedno...

[LM]

4Kukla Kuklovič: Dík

Mam na PCI ATA100/RAID řadič --> skusim si s tim trochu pohrát