Citace:
On the specifications front, several tidbits were pointed at to give enthusiasts some tea leaves to stir. In the configuration demoed in San Francisco, each R600 is said to have used 200W, be comprised of 320 "multiply-accumulate units", and between the two units on display be capable of a total of one teraflop of math power. While it's not clear yet which bits are definite AMD marketing language and which are reporters trying to invent language to report with, it would appear to us likely that AMD will also be joining the scalar bandwagon, and that to reach 1 teraflop of compute power with 320 ALUs x 2, would most likely imply a clock of roughly 800MHz operating on MADD units. Going well back to early rumours and reporting of R600 last spring, and adding today's 320 ALUs, this would begin to look like a modified/improved version of Xenos at 4 arrays of 16, with the 5D ALUs improved to be scalar and fully MADD. However, AMD's generosity of information today did not extend quite so far as that, and some actual poking and prodding would be required to confirm this.